Microelectronic circuits must be tested for faults after their fabrication. This relates in particular to memory units such as, for example, SDRAMs which require a comprehensive test to be carried out in a test device in order to prevent malfunctions as far as possible after their fabrication.
When a memory unit to be tested is tested, “actual data” is read out of the memory unit to be tested and then compared with “setpoint data” in a comparator unit of the test device. The costs of a comparator unit increase here if data rates increase because an increase in the data rate makes it necessary to reduce a chronological inaccuracy of the comparator unit.
Automatic test devices, which are also referred to as testers, make it possible, for example, to measure values to be registered such as a maximum frequency at which a memory unit functions without faults.
It is expedient that test devices operate automatically, memory units to be tested being tested with a minimum frequency and minimum accuracy, but on the other hand the largest possible number of circuit components (chips) which contain memory units are tested simultaneously.
The present generations of integrated electronic components such as, for example, memory units disadvantageously require test devices which are very costly owing to the high minimum frequency which must be made available in a test.
On the other hand, there are essentially two groups of malfunctions which are to be registered by testing memory units to be tested:                (i) an information item has not been correctly written into the memory cell array of a memory unit to be tested or not correctly read out from the memory cell array of the memory unit to be tested; and        (ii) an output unit of the memory unit to be tested is faulty.        
The output unit which is designated above under item (ii) or its efficiency can only be tested at specified high clock and data frequencies, while the memory cell array of the memory unit to be tested can also be tested reliably at relatively low clock and data frequencies and at relatively low speeds.
Thus, for example in currently customary methods which operate in the DDR (Double Data Rate) mode, data registers are read out of the memory unit to be tested and written into the memory unit to be tested, a data rate being used which is doubled by the fact that data is transferred not only at a rising clock edge but also at a falling clock edge.
This double data rate is generated component-internally by virtue of the fact that at least two bits from the memory cell array of the memory unit to be tested are read out simultaneously per data connection and buffered upstream of the output unit (referred to as a prefetch), and said bits are then output successively, the data rate at this specific output unit corresponding to at least twice the clock frequency, while the memory cell array is operated with a single (low or original) clock frequency. It is to be noted that a corresponding procedure is executed when the memory cell array is written to.
The same applies to future-generation memory units to be tested or standard versions with a relatively high number of buffer units (relatively high number of prefetch units).
A disadvantage of conventional methods for testing memory units to be tested is thus that although conventional test devices can make available a required clock frequency for the memory unit to be tested, a chronological inaccuracy of a comparator unit is however so high that the increased data rate obtained cannot be coped with.
It is thus inexpedient that there is a need for a costly test device with a comparator unit whose chronological inaccuracy is small enough to test the memory unit at an increased data rate.
It is a disadvantage that in general it is not possible to use test devices which are available in a cost-effective manner and which are operated with a simple, low clock frequency.